configure clock register
| EFUSE_CLK_FORCE_GATING | force efuse clk gating |
| EFUSE_CLK_FORCE_NOGATING | force efuse clk nogating |
| CK8M_DIV_SEL_VLD | used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk |
| CK8M_DIV | CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024. |
| ENB_CK8M | disable CK8M and CK8M_D256_OUT |
| ENB_CK8M_DIV | 1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256 |
| DIG_XTAL32K_EN | enable CK_XTAL_32K for digital core (no relationship with RTC core) |
| DIG_CLK8M_D256_EN | enable CK8M_D256_OUT for digital core (no relationship with RTC core) |
| DIG_CLK8M_EN | enable CK8M for digital core (no relationship with RTC core) |
| CK8M_DIV_SEL | divider = reg_ck8m_div_sel + 1 |
| XTAL_FORCE_NOGATING | XTAL force no gating during sleep |
| CK8M_FORCE_NOGATING | CK8M force no gating during sleep |
| CK8M_DFREQ | CK8M_DFREQ |
| CK8M_FORCE_PD | CK8M force power down |
| CK8M_FORCE_PU | CK8M force power up |
| XTAL_GLOBAL_FORCE_GATING | force global xtal gating |
| XTAL_GLOBAL_FORCE_NOGATING | force global xtal no gating |
| FAST_CLK_RTC_SEL | fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M |
| ANA_CLK_RTC_SEL | select slow clock |